1. Field of the Invention
The present invention relates to an electronic parts packaging structure and a method of manufacturing the same and, more particularly, an electronic parts packaging structure in which semiconductor chips, etc. are mounted on a wiring substrate in a state that they are buried in an insulating film and a method of manufacturing the same.
2. Description of the Related Art
The development of the LSI technology as a key technology to implement multimedia devices is proceeding steadily to a higher speed and a larger capacity of the data transmission. According to this, a higher density of the packaging technology as interfaces between the LSI and electronic devices is also proceeding.
In reply to the request of a further higher density, the multichip package (semiconductor device) in which a plurality of semiconductor chips are laminated three-dimensionally on the substrate and packaged has been developed. As an example, in Patent Application Publication (KOKAI) 2001-196525 (Patent Literature 1), it is set forth that the semiconductor device having the structure in which a plurality of semiconductor chips are packaged three-dimensionally on the wiring substrate in a state that they are buried in the insulating layer and then the semiconductor chips are bonded to the wiring patterns, which are formed in a multi-layered fashion via the insulating layers, by the flip-chip bonding.
Also, in Patent Application Publication (KOKAI) 2001-274034 (Patent Literature 2), it is set forth that, in order to package the electronic parts at a high density and to shield the electronic parts from electronic noises that affect the electronic parts, the electronic parts package which contains the structure, in which the electronic parts are packaged in the concave portions provided to the core material and inner wall surfaces and bottom surfaces of the concave portions are made of the conductive metal, and in which a plurality of electronic parts are packaged.
However, in above Patent Literature 1, no consideration is given to the event that, when the interlayer insulating film is to be formed on the mounted semiconductor chips, such interlayer insulating film is formed to have differences in level due to a thickness of the semiconductor chips. In other words, if the steps are generated on the interlayer insulating film on the semiconductor chips, a focus margin in the photolithography applied in the step of forming the wiring patterns on this interlayer insulating film is reduced. Therefore, it is possible that it become difficult to form desired resist patterns with good precision.
In addition, differences in level also appear on the wiring patterns formed on the interlayer insulating film. Therefore, it is possible that, when the semiconductor chips are bonded to the wiring patterns by the flip-chip bonding, the reliability of such bonding is lowered.
Also, in Patent Literature 2, no consideration is given to the above problems caused when the semiconductor chips being buried in the interlayer insulating film are packaged over the wiring substrate having no concave portion thereon, in the technology of providing the concave portions on the core member and packaging the electronic parts in the concave portions.